In a dynamic random access memory (DRAM), a plurality of memory cells are formed in a matrix manner on a substrate. Each memory cell in the DRAM includes at least one transistor and at least one capacitor. For high density, a memory cell typically includes a single capacitor and either one or as few transistors as needed to provide conduction between the capacitor and first level read/write circuits, while conserving chip area. In present DRAMs, the capacitor of the memory cell is constructed according to one of two different, alternative technologies in which it is located either in the lower part of a deep trench, or stacked in a level above the substrate-level transistor. DRAMs having stacked capacitors generally have less planarity than deep trench capacitors. Therefore, where a high degree of planarity is needed, trench capacitor structures are preferred.
In DRAMs as well as in other circuits, it is desirable that a semiconductor chip hold as many circuits and memory cells as possible per unit area. However, while the size of capacitors and devices shrinks from one generation to the next, the operating voltages, logic levels and minimum sensing currents are not reduced at the same rate, such that proportionally greater capacitance is required from the memory cell capacitor in each succeeding generation. One way to increase capacitance is by reducing the thickness of the capacitor dielectric. However, if the capacitor dielectric becomes too thin, an unacceptable number of capacitors in the chip can exhibit excessively high leakage across the dielectric, and therefore render the chip unusable.
Higher capacitance can be achieved without reducing dielectric thickness by using high-K dielectric materials having higher dielectric constants than those conventionally used in DRAMs, of which silicon dioxide is principally used. Amorphous silicon dioxide has a dielectric constant of 3.9. However, forming a high-K dielectric material in a trenched structure poses challenges. High-K dielectric materials have usually been used only in conjunction with stacked capacitor memory cells. But since the trench structure is needed to achieve surface flatness in many circuits, there is a need to incorporate a high-K dielectric node dielectric in a trench capacitor structure. It would further be desirable to form the node dielectric and device gate dielectric of a trench DRAM memory cell at the same time. It would further be desirable to incorporate such trench capacitor node dielectric and device gate dielectric formed at the same time in a DRAM cell having a vertical transistor located above the trench capacitor.